ASML's Q4 2025 earnings call provides the sixth independent confirmation of structural memory supply tightening across the semiconductor equipment and memory manufacturing chain.

DRAM as the AI Bottleneck

CEO Christophe Fouquet explicitly identified DRAM as the bottleneck for AI deployment, stating that memory customers are "breaking ground almost every week" on new capacity. DRAM prices are rising, with 2026 supply characterized as tight. This corroborates prior evidence from Samsung (DRAM/HBM ASP +40% Q/Q, "tight undersupply through 2026-2027"), Western Digital (NAND shifting to multi-year supply agreements), Seagate (nearline fully allocated through CY2026), and Lam Research (NAND growing faster than expected).

Wafer Intensity Surge

ASML disclosed that NVIDIA's wafer consumption per AI product will increase 4x by 2027—from 2.5 wafers per product to 10 wafers. This structural shift in silicon intensity explains the capacity scramble: even with productivity improvements, absolute wafer demand is accelerating.

Demand Outpacing Productivity Gains

Despite 40% productivity improvements in EUV tools, ASML is shipping more tools, not fewer. The company accepted its first High NA EUV system (Twinscan EXE:5200B) for high-volume manufacturing. Management confirmed that demand growth is outrunning productivity gains—indicating structural, not cyclical, capacity expansion.

Guidance and Capital Allocation

ASML issued FY2026 revenue guidance of EUR 34-39 billion (gross margin 51-53%) and announced a EUR 12 billion share buyback. The company reaffirmed its 2030 revenue targets, signaling confidence in long-term demand visibility. A 1,700-person engineering reorganization was framed as a complexity reduction to improve agility, not a cost-cutting response to demand weakness.

Cross-Ticker Signal Convergence

This filing is the seventh data point in an accumulating pattern: Samsung's multiyear HBM supply contracts, Western Digital's NAND agreements, Seagate's 2027 bookings, Lam's unplanned fab announcements, and Apple's confirmation of TSMC advanced-node constraints all point to the same supply-demand imbalance. Each filing alone is routine disclosure. Together, they describe a memory supply chain operating at capacity limits with pricing power intact.

The 4x wafer intensity figure represents a permanent demand base expansion, not a cyclical upswing. Memory equipment suppliers and DRAM manufacturers are breaking ground weekly—a pace that suggests consensus EPS models may not yet reflect the magnitude of this capex cycle.